In a semiconductor test process, an electrical characteristics test for detecting a defective product is performed by bringing probes having conductivity into contact with a semiconductor wafer before dicing (wafer level test). When the wafer level test is performed, to transfer a test signal to the semiconductor wafer, a probe card housing a large number of probes is used. In the wafer level test, the probes are individually brought into contact with each of dies on the semiconductor wafer while the dies are scanned by the probe card. Because hundreds to tens of thousands of dies are formed on the semiconductor wafer, it takes considerable time to test one semiconductor wafer. Thus, an increase in the number of dies causes higher cost.
To solve the problems of the wafer level test described above, in recent years, a method (full wafer level test) is also used in which hundreds to tens of thousands of probes are collectively brought into contact with all or at least about ¼ to ½ of dies on a semiconductor wafer (see, for example, Patent Document 1). In this method, to accurately bring the probes into contact with electrodes on the semiconductor wafer, there are proposed a technology for maintaining positional accuracy of tips of probes by accurately keeping the parallelism or the flatness of a probe card with respect to a surface of the semiconductor wafer and a technology for highly accurately aligning a semiconductor wafer (see, for example, Patent Document 2 or 3).
FIG. 16 is a diagram schematically illustrating a configuration example of a probe card applied to the wafer level test described above. A probe card 401 illustrated in the figure includes a probe head 403 that houses a plurality of probes 402 arranged in accordance with an arrangement pattern of electrodes on a semiconductor wafer, a space transformer 404 that transforms a pitch of a fine wiring pattern on the prove head 403, an interposer 405 that relays wiring w put out from the space transformer 404, a leaf spring 406 that holds the probe head, a wiring substrate 407 that connects the wiring w relayed by the interposer 405 to a test apparatus, a connector 408 that is arranged on the wiring substrate 407 and is connected to the test apparatus side that generates a test signal, and a reinforcing member 409 that reinforces the wiring substrate 407.    Patent Document 1: Japanese Patent Application Publication No. 2001-524258    Patent Document 2: Japanese Patent No. 3386077    Patent Document 3: Japanese Laid-open Patent Publication No. 2005-164600